diff -Naur u-boot-1.3.3/board/at91boff/at91boff.c u-boot-1.3.3.new/board/at91boff/at91boff.c --- u-boot-1.3.3/board/at91boff/at91boff.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/board/at91boff/at91boff.c 2008-06-21 10:03:26.000000000 +0200 @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2002 + * Boff corporation + * Lucjan Bryndza + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* Enable Ctrlc */ + console_init_f (); + + /* Correct IRDA resistor problem */ + /* Set PA23_TXD in Output */ + ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of AT91RM9200-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_DRIVER_ETHER +#if defined(CONFIG_CMD_NET) + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = ste100p_InitPhy; + p_phyops->IsPhyConnected = ste100p_IsPhyConnected; + p_phyops->GetLinkSpeed = ste100p_GetLinkSpeed; + p_phyops->AutoNegotiate = ste100p_AutoNegotiate; +} + +#endif +#endif /* CONFIG_DRIVER_ETHER */ + +//Configure MAC address +#if defined(CONFIG_CMD_NET) +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + int i; + char *tmp,*end; + tmp = getenv("ethaddr"); + if (tmp==NULL) + { + printf("MAC address not set, networking is not " + "operational\n"); + return 0; + } + bd_t bd; + for (i=0; i<6; i++) + { + bd.bi_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + printf("Using MAC address %02X:%02X:%02X:%02X:%02X:%02X\n", + bd.bi_enetaddr[0],bd.bi_enetaddr[1],bd.bi_enetaddr[2], + bd.bi_enetaddr[3],bd.bi_enetaddr[4],bd.bi_enetaddr[5]); + return eth_init(&bd); +} +#endif +#endif + diff -Naur u-boot-1.3.3/board/at91boff/config.mk u-boot-1.3.3.new/board/at91boff/config.mk --- u-boot-1.3.3/board/at91boff/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/board/at91boff/config.mk 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff -Naur u-boot-1.3.3/board/at91boff/flash.c u-boot-1.3.3.new/board/at91boff/flash.c --- u-boot-1.3.3/board/at91boff/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/board/at91boff/flash.c 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,502 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush(void); + + +/* Flash Organization Structure */ +typedef struct OrgDef +{ + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgAT49BV16x4[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ + { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV16x4A[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV6416[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ +}; + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/* AT49BV1614A Codes */ +#define FLASH_CODE1 0xAA +#define FLASH_CODE2 0x55 +#define ID_IN_CODE 0x90 +#define ID_OUT_CODE 0xF0 + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 +#define CMD_SECTOR_UNLOCK 0x0070 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ +void flash_identification (flash_info_t * info) +{ + volatile u16 manuf_code, device_code, add_device_code; + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_IN_CODE; + + manuf_code = *(volatile u16 *) CFG_FLASH_BASE; + device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); + add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_OUT_CODE; + + /* Vendor type */ + info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; + printf ("Atmel: "); + + if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + if ((add_device_code & FLASH_TYPEMASK) == + (ATM_ID_BV1614A & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; + printf ("AT49BV1614A (16Mbit)\n"); + } else { /* AT49BV1614 Flash */ + info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; + printf ("AT49BV1614 (16Mbit)\n"); + } + + } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; + printf ("AT49BV6416 (64Mbit)\n"); + } +} + +ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) +{ + int i, nb_sectors = 0; + + for (i=0; istart[sector]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + *addr = CMD_SECTOR_UNLOCK; +} + + +ulong flash_init (void) +{ + int i, j, k; + unsigned int flash_nb_blocks, sector; + unsigned int start_address; + OrgDef *pOrgDef; + + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_identification (&flash_info[i]); + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + pOrgDef = OrgAT49BV16x4; + flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ + + pOrgDef = OrgAT49BV16x4A; + flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + pOrgDef = OrgAT49BV6416; + flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); + } else { + flash_nb_blocks = 0; + pOrgDef = OrgAT49BV16x4; + } + + flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); + memset (flash_info[i].protect, 0, flash_info[i].sector_count); + + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + + sector = 0; + start_address = flashbase; + flash_info[i].size = 0; + + for (j = 0; j < flash_nb_blocks; j++) { + for (k = 0; k < pOrgDef[j].sector_number; k++) { + flash_info[i].start[sector++] = start_address; + start_address += pOrgDef[j].sector_size; + flash_info[i].size += pOrgDef[j].sector_size; + } + } + + size += flash_info[i].size; + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + /* Unlock all sectors at reset */ + for (j=0; jflash_id & FLASH_VENDMASK) { + case (ATM_MANUFACT & FLASH_VENDMASK): + printf ("Atmel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (ATM_ID_BV1614 & FLASH_TYPEMASK): + printf ("AT49BV1614 (16Mbit)\n"); + break; + case (ATM_ID_BV1614A & FLASH_TYPEMASK): + printf ("AT49BV1614A (16Mbit)\n"); + break; + case (ATM_ID_BV6416 & FLASH_TYPEMASK): + printf ("AT49BV6416 (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + return; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (ATM_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + }; + + if ((int) src & 1) { + printf ("unaligned source not supported\n"); + return ERR_ALIGN; + }; + + wp = addr; + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << + 8); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + }; + + return ERR_OK; +} diff -Naur u-boot-1.3.3/board/at91boff/Makefile u-boot-1.3.3.new/board/at91boff/Makefile --- u-boot-1.3.3/board/at91boff/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/board/at91boff/Makefile 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := at91boff.o flash.o partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -Naur u-boot-1.3.3/board/at91boff/partition.c u-boot-1.3.3.new/board/at91boff/partition.c --- u-boot-1.3.3/board/at91boff/partition.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/board/at91boff/partition.c 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + /*define the dataflash offsets*/ + {DATAFLASH_LOADER_BASE /* 0 */, DATAFLASH_UBOOT_BASE - 1,FLAG_PROTECT_SET,0 ,"Darrell loader"}, + {DATAFLASH_UBOOT_BASE, DATAFLASH_ENV_UBOOT_BASE - 1,FLAG_PROTECT_SET, 0,"U-boot"}, +// {DATAFLASH_ENV_UBOOT_BASE, DATAFLASH_KERNEL_BASE - 1,FLAG_PROTECT_CLEAR,0 ,"Environment"}, + {DATAFLASH_ENV_UBOOT_BASE, 512*264-1,FLAG_PROTECT_CLEAR,0 ,"Environment"}, +// {DATAFLASH_KERNEL_BASE, 0x1fffff,FLAG_PROTECT_CLEAR, 0,"Kernel"}, +}; diff -Naur u-boot-1.3.3/board/at91boff/u-boot.lds u-boot-1.3.3.new/board/at91boff/u-boot.lds --- u-boot-1.3.3/board/at91boff/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/board/at91boff/u-boot.lds 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-1.3.3/cpu/arm920t/at91rm9200/atmel_mci.c u-boot-1.3.3.new/cpu/arm920t/at91rm9200/atmel_mci.c --- u-boot-1.3.3/cpu/arm920t/at91rm9200/atmel_mci.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/cpu/arm920t/at91rm9200/atmel_mci.c 2008-06-21 10:16:17.000000000 +0200 @@ -0,0 +1,672 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * Modification from AVR32 to AT91RM9200 by Lucjan Bryndza + * Also support Atmel hardware fix bswap in at91rm9200 + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_MMC + +#include +#include + +#include +#include +#include +#include + +#include "atmel_mci.h" + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + +#ifndef CFG_MMC_CLK_OD +#define CFG_MMC_CLK_OD 150000 +#endif + +#ifndef CFG_MMC_CLK_PP +#define CFG_MMC_CLK_PP 5000000 +#endif + +#ifndef CFG_MMC_OP_COND +#define CFG_MMC_OP_COND 0x00100000 +#endif + +#define MMC_DEFAULT_BLKLEN 512 +#define MMC_DEFAULT_RCA 1 + + + + + + +static unsigned int mmc_rca; +static int mmc_card_is_sd; +static int mmc_card_is_sdhc; +static block_dev_desc_t mmc_blkdev; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + return &mmc_blkdev; +} + +static void mci_set_mode(unsigned long hz, unsigned long blklen) +{ + unsigned long bus_hz; + unsigned long clkdiv; + + bus_hz = AT91C_MASTER_CLOCK; + clkdiv = (bus_hz / hz) / 2 - 1; + + pr_debug("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); + + if (clkdiv & ~255UL) { + clkdiv = 255; + printf("mmc: clock %lu too low; setting CLKDIV to 255\n", + hz); + } + + blklen &= 0xfffc; + mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) + | MMCI_BF(BLKLEN, blklen))); +// | MMCI_BIT(RDPROOF) +// | MMCI_BIT(WRPROOF))); +} + +#define RESP_NO_CRC 1 +#define R1 MMCI_BF(RSPTYP, 1) +#define R2 MMCI_BF(RSPTYP, 2) +#define R3 (R1 | RESP_NO_CRC) +#define R6 R1 +#define R7 R3 +#define NID MMCI_BF(MAXLAT, 0) +#define NCR MMCI_BF(MAXLAT, 1) +#define TRCMD_START MMCI_BF(TRCMD, 1) +#define TRDIR_READ MMCI_BF(TRDIR, 1) +#define TRTYP_BLOCK MMCI_BF(TRTYP, 0) +#define INIT_CMD MMCI_BF(SPCMD, 1) +#define OPEN_DRAIN MMCI_BF(OPDCMD, 1) + +#define ERROR_FLAGS (MMCI_BIT(DTOE) \ + | MMCI_BIT(RDIRE) \ + | MMCI_BIT(RENDE) \ + | MMCI_BIT(RINDE) \ + | MMCI_BIT(RTOE)) + +static int +mmc_cmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long *response = resp; + int i, response_words = 0; + unsigned long error_flags; + u32 status; + + pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", + cmd, arg, flags); + + error_flags = ERROR_FLAGS; + if (!(flags & RESP_NO_CRC)) + error_flags |= MMCI_BIT(RCRCE); + + flags &= ~MMCI_BF(CMDNB, ~0UL); + + if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP) + response_words = 1; + else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP) + response_words = 4; + + mmci_writel(ARGR, arg); + mmci_writel(CMDR, cmd | flags); + do { + udelay(40); + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(CMDRDY))); + + pr_debug("mmc: status 0x%08lx\n", status); + + if (status & ERROR_FLAGS) { + printf("mmc: command %lu failed (status: 0x%08lx)\n", + cmd, status); + return -EIO; + } + + if (response_words) + pr_debug("mmc: response:"); + + for (i = 0; i < response_words; i++) { + response[i] = mmci_readl(RSPR); + pr_debug(" %08lx", response[i]); + } + pr_debug("\n"); + + return 0; +} + +static int mmc_acmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long aresp[4]; + int ret; + + /* + * Seems like the APP_CMD part of an ACMD has 64 cycles max + * latency even though the ACMD part doesn't. This isn't + * entirely clear in the SD Card spec, but some cards refuse + * to work if we attempt to use 5 cycles max latency here... + */ + ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, + R1 | NCR | (flags & OPEN_DRAIN)); + if (ret) + return ret; + if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD) + return -ENODEV; + + ret = mmc_cmd(cmd, arg, resp, flags); + return ret; +} + +static unsigned long +mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + u32 status; + + if (blkcnt == 0) + return 0; + + pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + + for (i = 0; i < blkcnt; i++, start++) { + ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, + (mmc_card_is_sdhc==0)?(start*mmc_blkdev.blksz):(start), + resp,(R1 | NCR | TRCMD_START | TRDIR_READ + | TRTYP_BLOCK)); + if (ret) goto fail; + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(SR); + if (status & (ERROR_FLAGS | MMCI_BIT(OVRE))) + goto fail; + } while (!(status & MMCI_BIT(RXRDY))); + + if (status & MMCI_BIT(RXRDY)) { + //AT91RM9200 Hardware bug + data = swab32(mmci_readl(RDR)); + /* pr_debug("%x\n", data); */ + *buffer++ = data; + wordcount++; + } + } while(wordcount < (mmc_blkdev.blksz / 4)); + + pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(BLKE))); + + //putc('.'); + } + +out: + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + return i; + +fail: + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + printf("mmc: bread failed, card status = %08x\n", card_status); + goto out; +} + +static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = resp[2] >> 24; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 16; + cid->psn = (resp[2] << 16) | (resp[3] >> 16); + cid->mdt = resp[3] >> 8; +} + +static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = 0; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 24; + cid->psn = (resp[2] << 8) | (resp[3] >> 24); + cid->mdt = (resp[3] >> 8) & 0x0fff; +} + + + +/* + * Given a 128-bit response, decode to our card CSD structure. + */ +static int mmc_parse_csd(struct mmc_csd *csd,unsigned long *resp) +{ + csd->csd_structure = UNSTUFF_BITS(resp,126,2); + csd->spec_vers = UNSTUFF_BITS(resp,122,4); + csd->taac = UNSTUFF_BITS(resp,112,8); + csd->nsac = UNSTUFF_BITS(resp,104,8); + csd->tran_speed = UNSTUFF_BITS(resp,96,8); + csd->ccc = UNSTUFF_BITS(resp,84,12); + csd->read_bl_len = UNSTUFF_BITS(resp,80,4); + csd->read_bl_partial = UNSTUFF_BITS(resp,79,1); + csd->write_blk_misalign = UNSTUFF_BITS(resp,78,1); + csd->read_blk_misalign = UNSTUFF_BITS(resp,77,1); + csd->dsr_imp = UNSTUFF_BITS(resp,76,1); + if(csd->csd_structure==0) + { + //Structure version 1 + csd->c_size = UNSTUFF_BITS(resp,62,12); + csd->vdd_r_curr_min = UNSTUFF_BITS(resp,59,3); + csd->vdd_r_curr_max = UNSTUFF_BITS(resp,56,3); + csd->vdd_w_curr_min = UNSTUFF_BITS(resp,53,3); + csd->vdd_w_curr_max = UNSTUFF_BITS(resp,50,3); + csd->c_size_mult = UNSTUFF_BITS(resp,47,3); + } + else + { + //Structure version 2 + csd->c_size = UNSTUFF_BITS(resp,48,22); + } + csd->sector_size = UNSTUFF_BITS(resp,39,7); + csd->wp_grp_size = UNSTUFF_BITS(resp,32,7); + csd->wp_grp_enable = UNSTUFF_BITS(resp,31,1); + csd->default_ecc = UNSTUFF_BITS(resp,29,2); + csd->r2w_factor = UNSTUFF_BITS(resp,26,3); + csd->write_bl_len = UNSTUFF_BITS(resp,22,4); + csd->write_bl_partial = UNSTUFF_BITS(resp,21,1); + csd->file_format_grp = UNSTUFF_BITS(resp,15,1); + csd->copy = UNSTUFF_BITS(resp,14,1); + csd->perm_write_protect = UNSTUFF_BITS(resp,13,1); + csd->tmp_write_protect = UNSTUFF_BITS(resp,12,1); + csd->file_format = UNSTUFF_BITS(resp,10,2); + csd->ecc = UNSTUFF_BITS(resp,8,2); + csd->crc = UNSTUFF_BITS(resp,1,7); + return 0; +} + + +static void mmc_dump_cid(const struct mmc_cid *cid) +{ + printf("Manufacturer ID: %02lX\n", cid->mid); + printf("OEM/Application ID: %04lX\n", cid->oid); + printf("Product name: %s\n", cid->pnm); + printf("Product Revision: %lu.%lu\n", + cid->prv >> 4, cid->prv & 0x0f); + printf("Product Serial Number: %lu\n", cid->psn); + printf("Manufacturing Date: %02lu/%02lu\n", + cid->mdt >> 4, cid->mdt & 0x0f); +} + +static void mmc_dump_csd(const struct mmc_csd *csd) +{ + //unsigned long *csd_raw = (unsigned long *)csd; + //printf("CSD data: %08lx %08lx %08lx %08lx\n", + // csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); + unsigned int card_capacity; + printf("CSD structure version: 1.%u\n", csd->csd_structure); + printf("MMC System Spec version: %u\n", csd->spec_vers); + printf("Card command classes: %03x\n", csd->ccc); + printf("Read block length: %u\n", 1 << csd->read_bl_len); + if (csd->read_bl_partial) + puts("Supports partial reads\n"); + else + puts("Does not support partial reads\n"); + printf("Write block length: %u\n", 1 << csd->write_bl_len); + if (csd->write_bl_partial) + puts("Supports partial writes\n"); + else + puts("Does not support partial writes\n"); + if (csd->wp_grp_enable) + printf("Supports group WP: %u\n", csd->wp_grp_size + 1); + else + puts("Does not support group WP\n"); + if(csd->csd_structure==0) + { + card_capacity = (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * + (1 << csd->read_bl_len); + card_capacity /= (1024*1024); + } + else + { + card_capacity = csd->c_size/2; + } + printf("Card capacity: %u MB\n",card_capacity); + printf("File format: %u/%u\n", + csd->file_format_grp, csd->file_format); + puts("Write protection: "); + if (csd->perm_write_protect) + puts(" permanent"); + if (csd->tmp_write_protect) + puts(" temporary"); + putc('\n'); +} + +static int mmc_idle_cards(void) +{ + int ret; + + /* Reset and initialize all cards */ + ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); + if (ret) + return ret; + + /* Keep the bus idle for 74 clock cycles */ + return mmc_cmd(0, 0, NULL, INIT_CMD); +} + +static int sd_init_card(struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 1000; i++) { + ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, + resp, R3 | NID); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); + if (ret) + return ret; + sd_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Get RCA of the card that responded */ + ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + if (ret) + return ret; + + mmc_rca = resp[0] >> 16; + if (verbose) + printf("SD Card detected (RCA %u)\n", mmc_rca); + mmc_card_is_sd = 1; + return 0; +} + +static int sdhc_init_card(struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + + ret = mmc_cmd(MMC_CMD_SD_SEND_IF_COND, 0x00000122, resp, R7 | NID); + if (ret || resp[0]!=0x122) + return ret; + + for (i = 0; i < 1000; i++) { + ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, 0x40000000 , + resp, R3 | NID); + if( ret==0 && (resp[0] & 0x80000000) && (resp[0] & 0x40000000)==0x40000000 ) + { + mmc_card_is_sdhc = 1; + break; + } + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); + if (ret) + return ret; + sd_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Get RCA of the card that responded */ + ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + if (ret) + return ret; + + mmc_rca = resp[0] >> 16; + if (verbose) + printf("SDv2/SDHC Card detected (RCA %u) SDHC flag %d\n", mmc_rca,mmc_card_is_sdhc); + mmc_card_is_sd = 1; + return 0; +} + + +static int mmc_init_card(struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 1000; i++) { + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp, + R3 | NID | OPEN_DRAIN); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + /* Get CID of all cards. FIXME: Support more than one card */ + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); + if (ret) + return ret; + mmc_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Set Relative Address of the card that responded */ + ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, + R1 | NCR | OPEN_DRAIN); + return ret; +} + +static void mci_set_data_timeout(struct mmc_csd *csd) +{ + static const unsigned int dtomul_to_shift[] = { + 0, 4, 7, 8, 10, 12, 16, 20, + }; + static const unsigned int taac_exp[] = { + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, + }; + static const unsigned int taac_mant[] = { + 0, 10, 12, 13, 15, 60, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80, + }; + unsigned int timeout_ns, timeout_clks; + unsigned int e, m; + unsigned int dtocyc, dtomul; + unsigned int shift; + u32 dtor; + + e = csd->taac & 0x07; + m = (csd->taac >> 3) & 0x0f; + + timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; + timeout_clks = csd->nsac * 100; + + timeout_clks += (((timeout_ns + 9) / 10) + * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; + if (!mmc_card_is_sd) + timeout_clks *= 10; + else + timeout_clks *= 100; + + dtocyc = timeout_clks; + dtomul = 0; + while (dtocyc > 15 && dtomul < 8) { + dtomul++; + shift = dtomul_to_shift[dtomul]; + dtocyc = (timeout_clks + (1 << shift) - 1) >> shift; + } + + if (dtomul >= 8) { + dtomul = 7; + dtocyc = 15; + puts("Warning: Using maximum data timeout\n"); + } + + dtor = (MMCI_BF(DTOMUL, dtomul) + | MMCI_BF(DTOCYC, dtocyc)); + mmci_writel(DTOR, dtor); + + printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n", + dtocyc << shift, dtor); +} + +int mmc_init(int verbose) +{ + struct mmc_cid cid; + struct mmc_csd csd; + unsigned long csd_raw[4]; + unsigned int max_blksz; + int ret; + *AT91C_PIOA_PDR = (1<<27)|(1<<28)|(1<<29); /* GPIO to MMC Interface */ + *AT91C_PMC_PCER = 1 << 10; /* Peripheral Clock Enable Register */ + /* Initialize controller */ + mmci_writel(CR, MMCI_BIT(SWRST)); + mmci_writel(CR, MMCI_BIT(MCIEN)); + mmci_writel(DTOR, 0x5f); + mmci_writel(IDR, ~0UL); + mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + + mmc_card_is_sd = 0; + mmc_card_is_sdhc = 0; + ret = sdhc_init_card(&cid,verbose); + if(ret) + { + ret = sd_init_card(&cid, verbose); + if (ret) + { + mmc_rca = MMC_DEFAULT_RCA; + ret = mmc_init_card(&cid, verbose); + } + } + if (ret) + return ret; + + /* Get CSD from the card */ + ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, csd_raw, R2 | NCR); + mmc_parse_csd(&csd,csd_raw); + if (ret) + return ret; + if (verbose) + mmc_dump_csd(&csd); + + mci_set_data_timeout(&csd); + + /* Initialize the blockdev structure */ + mmc_blkdev.if_type = IF_TYPE_MMC; + mmc_blkdev.part_type = PART_TYPE_DOS; + mmc_blkdev.block_read = mmc_bread; + sprintf((char *)mmc_blkdev.vendor, + "Man %02x%04x Snr %08x", + cid.mid, cid.oid, cid.psn); + strncpy((char *)mmc_blkdev.product, cid.pnm, + sizeof(mmc_blkdev.product)); + sprintf((char *)mmc_blkdev.revision, "%x %x", + cid.prv >> 4, cid.prv & 0x0f); + + /* + * If we can't use 512 byte blocks, refuse to deal with the + * card. Tons of code elsewhere seems to depend on this. + */ + max_blksz = 1 << csd.read_bl_len; + if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) { + printf("Card does not support 512 byte reads, aborting.\n"); + return -ENODEV; + } + mmc_blkdev.blksz = 512; + mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); + + mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); + +#if 0 + if (fat_register_device(&mmc_blkdev, 1)) + printf("Could not register MMC fat device\n"); +#else + init_part(&mmc_blkdev); +#endif + + return 0; +} + +int mmc_read(ulong src, uchar *dst, int size) +{ + return -ENOSYS; +} + +int mmc_write(uchar *src, ulong dst, int size) +{ + return -ENOSYS; +} + +int mmc2info(ulong addr) +{ + return 0; +} + +#endif /* CONFIG_MMC */ diff -Naur u-boot-1.3.3/cpu/arm920t/at91rm9200/atmel_mci.h u-boot-1.3.3.new/cpu/arm920t/at91rm9200/atmel_mci.h --- u-boot-1.3.3/cpu/arm920t/at91rm9200/atmel_mci.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/cpu/arm920t/at91rm9200/atmel_mci.h 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CPU_AT91_ATMEL_MCI_H__ +#define __CPU_AT91_ATMEL_MCI_H__ + +/* Atmel MultiMedia Card Interface (MCI) registers */ +#define MMCI_CR 0x0000 +#define MMCI_MR 0x0004 +#define MMCI_DTOR 0x0008 +#define MMCI_SDCR 0x000c +#define MMCI_ARGR 0x0010 +#define MMCI_CMDR 0x0014 +#define MMCI_RSPR 0x0020 +#define MMCI_RSPR1 0x0024 +#define MMCI_RSPR2 0x0028 +#define MMCI_RSPR3 0x002c +#define MMCI_RDR 0x0030 +#define MMCI_TDR 0x0034 +#define MMCI_SR 0x0040 +#define MMCI_IER 0x0044 +#define MMCI_IDR 0x0048 +#define MMCI_IMR 0x004c + +/* Bitfields in CR */ +#define MMCI_MCIEN_OFFSET 0 +#define MMCI_MCIEN_SIZE 1 +#define MMCI_MCIDIS_OFFSET 1 +#define MMCI_MCIDIS_SIZE 1 +#define MMCI_PWSEN_OFFSET 2 +#define MMCI_PWSEN_SIZE 1 +#define MMCI_PWSDIS_OFFSET 3 +#define MMCI_PWSDIS_SIZE 1 +#define MMCI_SWRST_OFFSET 7 +#define MMCI_SWRST_SIZE 1 + +/* Bitfields in MR */ +#define MMCI_CLKDIV_OFFSET 0 +#define MMCI_CLKDIV_SIZE 8 +#define MMCI_PWSDIV_OFFSET 8 +#define MMCI_PWSDIV_SIZE 3 +#define MMCI_RDPROOF_OFFSET 11 +#define MMCI_RDPROOF_SIZE 1 +#define MMCI_WRPROOF_OFFSET 12 +#define MMCI_WRPROOF_SIZE 1 +#define MMCI_PDCPADV_OFFSET 14 +#define MMCI_PDCPADV_SIZE 1 +#define MMCI_PDCMODE_OFFSET 15 +#define MMCI_PDCMODE_SIZE 1 +#define MMCI_BLKLEN_OFFSET 16 +#define MMCI_BLKLEN_SIZE 16 + +/* Bitfields in DTOR */ +#define MMCI_DTOCYC_OFFSET 0 +#define MMCI_DTOCYC_SIZE 4 +#define MMCI_DTOMUL_OFFSET 4 +#define MMCI_DTOMUL_SIZE 3 + +/* Bitfields in SDCR */ +#define MMCI_SCDSEL_OFFSET 0 +#define MMCI_SCDSEL_SIZE 4 +#define MMCI_SCDBUS_OFFSET 7 +#define MMCI_SCDBUS_SIZE 1 + +/* Bitfields in ARGR */ +#define MMCI_ARG_OFFSET 0 +#define MMCI_ARG_SIZE 32 + +/* Bitfields in CMDR */ +#define MMCI_CMDNB_OFFSET 0 +#define MMCI_CMDNB_SIZE 6 +#define MMCI_RSPTYP_OFFSET 6 +#define MMCI_RSPTYP_SIZE 2 +#define MMCI_SPCMD_OFFSET 8 +#define MMCI_SPCMD_SIZE 3 +#define MMCI_OPDCMD_OFFSET 11 +#define MMCI_OPDCMD_SIZE 1 +#define MMCI_MAXLAT_OFFSET 12 +#define MMCI_MAXLAT_SIZE 1 +#define MMCI_TRCMD_OFFSET 16 +#define MMCI_TRCMD_SIZE 2 +#define MMCI_TRDIR_OFFSET 18 +#define MMCI_TRDIR_SIZE 1 +#define MMCI_TRTYP_OFFSET 19 +#define MMCI_TRTYP_SIZE 2 + +/* Bitfields in RSPRx */ +#define MMCI_RSP_OFFSET 0 +#define MMCI_RSP_SIZE 32 + +/* Bitfields in SR/IER/IDR/IMR */ +#define MMCI_CMDRDY_OFFSET 0 +#define MMCI_CMDRDY_SIZE 1 +#define MMCI_RXRDY_OFFSET 1 +#define MMCI_RXRDY_SIZE 1 +#define MMCI_TXRDY_OFFSET 2 +#define MMCI_TXRDY_SIZE 1 +#define MMCI_BLKE_OFFSET 3 +#define MMCI_BLKE_SIZE 1 +#define MMCI_DTIP_OFFSET 4 +#define MMCI_DTIP_SIZE 1 +#define MMCI_NOTBUSY_OFFSET 5 +#define MMCI_NOTBUSY_SIZE 1 +#define MMCI_ENDRX_OFFSET 6 +#define MMCI_ENDRX_SIZE 1 +#define MMCI_ENDTX_OFFSET 7 +#define MMCI_ENDTX_SIZE 1 +#define MMCI_RXBUFF_OFFSET 14 +#define MMCI_RXBUFF_SIZE 1 +#define MMCI_TXBUFE_OFFSET 15 +#define MMCI_TXBUFE_SIZE 1 +#define MMCI_RINDE_OFFSET 16 +#define MMCI_RINDE_SIZE 1 +#define MMCI_RDIRE_OFFSET 17 +#define MMCI_RDIRE_SIZE 1 +#define MMCI_RCRCE_OFFSET 18 +#define MMCI_RCRCE_SIZE 1 +#define MMCI_RENDE_OFFSET 19 +#define MMCI_RENDE_SIZE 1 +#define MMCI_RTOE_OFFSET 20 +#define MMCI_RTOE_SIZE 1 +#define MMCI_DCRCE_OFFSET 21 +#define MMCI_DCRCE_SIZE 1 +#define MMCI_DTOE_OFFSET 22 +#define MMCI_DTOE_SIZE 1 +#define MMCI_OVRE_OFFSET 30 +#define MMCI_OVRE_SIZE 1 +#define MMCI_UNRE_OFFSET 31 +#define MMCI_UNRE_SIZE 1 + +/* Constants for DTOMUL */ +#define MMCI_DTOMUL_1_CYCLE 0 +#define MMCI_DTOMUL_16_CYCLES 1 +#define MMCI_DTOMUL_128_CYCLES 2 +#define MMCI_DTOMUL_256_CYCLES 3 +#define MMCI_DTOMUL_1024_CYCLES 4 +#define MMCI_DTOMUL_4096_CYCLES 5 +#define MMCI_DTOMUL_65536_CYCLES 6 +#define MMCI_DTOMUL_1048576_CYCLES 7 + +/* Constants for RSPTYP */ +#define MMCI_RSPTYP_NO_RESP 0 +#define MMCI_RSPTYP_48_BIT_RESP 1 +#define MMCI_RSPTYP_136_BIT_RESP 2 + +/* Constants for SPCMD */ +#define MMCI_SPCMD_NO_SPEC_CMD 0 +#define MMCI_SPCMD_INIT_CMD 1 +#define MMCI_SPCMD_SYNC_CMD 2 +#define MMCI_SPCMD_INT_CMD 4 +#define MMCI_SPCMD_INT_RESP 5 + +/* Constants for TRCMD */ +#define MMCI_TRCMD_NO_TRANS 0 +#define MMCI_TRCMD_START_TRANS 1 +#define MMCI_TRCMD_STOP_TRANS 2 + +/* Constants for TRTYP */ +#define MMCI_TRTYP_BLOCK 0 +#define MMCI_TRTYP_MULTI_BLOCK 1 +#define MMCI_TRTYP_STREAM 2 + +/* Bit manipulation macros */ +#define MMCI_BIT(name) \ + (1 << MMCI_##name##_OFFSET) +#define MMCI_BF(name,value) \ + (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \ + << MMCI_##name##_OFFSET) +#define MMCI_BFEXT(name,value) \ + (((value) >> MMCI_##name##_OFFSET)\ + & ((1 << MMCI_##name##_SIZE) - 1)) +#define MMCI_BFINS(name,value,old) \ + (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \ + << MMCI_##name##_OFFSET)) \ + | MMCI_BF(name,value)) + +/* Register access macros */ +#define mmci_readl(reg) \ + readl((void *)AT91_MCI_BASE + MMCI_##reg) +#define mmci_writel(reg,value) \ + writel((value), (void *)AT91_MCI_BASE + MMCI_##reg) + + + + +#define UNSTUFF_BITS(resp,start,size) \ + ({ \ + const int __size = size; \ + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int __off = 3 - ((start) / 32); \ + const int __shft = (start) & 31; \ + u32 __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off-1] << ((32 - __shft) % 32); \ + __res & __mask; \ + }) + + + +#endif /* __CPU_AT91_ATMEL_MCI_H__ */ diff -Naur u-boot-1.3.3/cpu/arm920t/at91rm9200/Makefile u-boot-1.3.3.new/cpu/arm920t/at91rm9200/Makefile --- u-boot-1.3.3/cpu/arm920t/at91rm9200/Makefile 2008-05-19 12:47:11.000000000 +0200 +++ u-boot-1.3.3.new/cpu/arm920t/at91rm9200/Makefile 2008-06-21 09:18:01.000000000 +0200 @@ -26,7 +26,7 @@ LIB = $(obj)lib$(SOC).a COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o serial.o usb.o spi.o + lxt972.o serial.o usb.o spi.o ste100p.o atmel_mci.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff -Naur u-boot-1.3.3/cpu/arm920t/at91rm9200/ste100p.c u-boot-1.3.3.new/cpu/arm920t/at91rm9200/ste100p.c --- u-boot-1.3.3/cpu/arm920t/at91rm9200/ste100p.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/cpu/arm920t/at91rm9200/ste100p.c 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2007 + * Author : Grzegorz Rajtar (McGregor) (mcgregor@blackmesaeast.com.pl) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +//#define DEBUG_ETHER + +#include +#include +#include + +#ifdef CONFIG_DRIVER_ETHER + +#if defined(CONFIG_CMD_NET) + +static void PhyReset(AT91PS_EMAC p_mac) +{ + static long init_wait = 0; + unsigned short IntValue; + unsigned Status; + unsigned int timeout; +#ifdef DEBUG_ETHER + printf("ste100p PhyReset \n"); +#endif + at91rm9200_EmacEnableMDIO (p_mac); + + + // first software reset the STE100P + at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); + udelay(1000); + IntValue |= STE100P_XCR_RESET; + + at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); + udelay(10000); + timeout = 100; + while (--timeout) + { + at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); + if ((IntValue & STE100P_XCR_RESET) != STE100P_XCR_RESET) + { +#ifdef DEBUG_ETHER + printf("PHY Reset OK\n"); +#endif + break; + } + udelay(1000); + } + + + IntValue = STE100P_ANA_FC | STE100P_ANA_TXF | STE100P_ANA_TXH | + STE100P_ANA_10F | STE100P_ANA_10H; + + + at91rm9200_EmacWritePhy (p_mac, STE100P_ANA_REG, &IntValue); + + //default configuration +#ifdef CONFIG_STE100P_OVERRIDE_HARDWARE + IntValue = STE100P_100CTR_ENDCR | STE100P_100CTR_ENRZI | STE100P_100CTR_EN4B5B; + IntValue &= ~(STE100P_100CTR_DISRER); + IntValue &= ~(STE100P_100CTR_ISOTX); + IntValue &= ~(STE100P_100CTR_DISMLT); + IntValue &= ~(STE100P_100CTR_DISCRM); + + at91rm9200_EmacWritePhy (p_mac, STE100P_100CTR_REG, &IntValue); + +#endif //CONFIG_STE100P_OVERRIDE_HARDWARE + + /* Disable PHY Interrupts */ + + at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue); + udelay(10000); + /* disable all interrypts from SE100P */ + + IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE | + STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE); + + at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue); + udelay(10000); + + at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); + + IntValue |= STE100P_XCR_AN | STE100P_XCR_RSTRT_AN; + at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); + + at91rm9200_EmacDisableMDIO (p_mac); +} + +/* + * Name: + * ste100p_Isolate + * Description: + * Isolates PHY + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id isolated successfuly + * FALSE- if error + */ + +unsigned int ste100p_Isolate (AT91PS_EMAC p_mac) +{ + unsigned int result = FALSE; + unsigned short IntValue; + + at91rm9200_EmacEnableMDIO (p_mac); + udelay(10000); + at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); + + IntValue |= STE100P_XCR_ISOLATE ;//| STE100P_XCR_PWRDN; + //IntValue &= ~STE100P_XCR_RESET; + //IntValue &= ~STE100P_XCR_AN; + + result = at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); + udelay(10000); + //Isolate is latch so we need to read once more the register + at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); + at91rm9200_EmacDisableMDIO (p_mac); + +#ifdef DEBUG_ETHER + printf("ste100p_Isolate [%d]\n", result); +#endif + return result; +} + + +/* + * Name: + * ste100p_IsPhyConnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id read successfully + * FALSE- if error + */ +unsigned int ste100p_IsPhyConnected (AT91PS_EMAC p_mac) +{ + unsigned short Id1, Id2; + unsigned int result = FALSE; + + at91rm9200_EmacEnableMDIO (p_mac); + udelay(10000); + do + { + Id1 = Id2 = 0; + udelay(10000); + at91rm9200_EmacReadPhy (p_mac, STE100P_PID1_REG, &Id1); + + udelay(10000); + at91rm9200_EmacReadPhy (p_mac, STE100P_PID2_REG, &Id2); + + Id2 = (Id2 & STE100P_PID2_PHYID_MASK) >> 6; + + if ((Id1 == STE100P_PID1_PHYID_VAL) && (Id2 == STE100P_PID2_PHYID_VAL)) + result = TRUE; + } while (!result); + + at91rm9200_EmacDisableMDIO (p_mac); +#ifdef DEBUG_ETHER + printf ("ste100p id1[0x%02x] id2[0x%02x]\r\n", Id1, Id2); +#endif + return result; +} + +/* + * Name: + * ste100p_GetLinkSpeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +UCHAR ste100p_GetLinkSpeed (AT91PS_EMAC p_mac) +{ + unsigned short stat; + int result = 0; + + result = at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &stat); + + if (!result) + return FALSE; + + if (!(stat & STE100P_XSR_LINK)) /* link status up? */ + { //last link failure is latched so reread STE100P_XSR_REG for new value + result = at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &stat); + if (!result || !(stat & STE100P_XSR_LINK)) + return FALSE; + } + + if (stat & STE100P_XSR_100TX_FULL) { + /*set Emac for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if (stat & STE100P_XSR_100TX) { + /*set Emac for 100BaseTX and Half Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + return TRUE; + } + + if (stat & STE100P_XSR_10T_FULL) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + + if (stat & STE100P_XSR_10T) { + /*set MII for 10BaseT and Half Duplex */ + p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + return TRUE; + } + + return FALSE; +} + + +/* + * Name: + * ste100p_Deisolate + * Description: + * deisolates PHY + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + */ + +void ste100p_Deisolate (AT91PS_EMAC p_mac) +{ + unsigned short IntValue; + + IntValue = STE100P_XCR_SPEED | STE100P_XCR_AN | + STE100P_XCR_COLLEN; + + at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); + + udelay(10000); + IntValue = STE100P_100CTR_EN4B5B | STE100P_100CTR_ENRZI | + STE100P_100CTR_ENDCR; + + at91rm9200_EmacWritePhy (p_mac, STE100P_100CTR_REG, &IntValue); + udelay(10000); + + + if ((IntValue & STE100P_XCR_ISOLATE) == STE100P_XCR_ISOLATE) + { + IntValue &= ~STE100P_XCR_ISOLATE; + at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); + udelay(10000); + //isolate is latch so read once more the register + at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); + udelay(10000); + } +} + +/* + * Name: + * ste100p_WaitForLink + * Description: + * waits for link with timeout + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * timeout - timeout in miliseconds + */ + +UCHAR ste100p_WaitForLink (AT91PS_EMAC p_mac, unsigned long timeout) +{ + unsigned long loop ; + unsigned short IntValue; + + loop = 0; + do + { + at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &IntValue); + if (IntValue & STE100P_XSR_LINK) + return TRUE; + + udelay(1000); + loop++; + if (loop > timeout) + break; + + } while (1); + + return FALSE; +} + +/* + * Name: + * ste100p_InitPhy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +UCHAR ste100p_InitPhy (AT91PS_EMAC p_mac) +{ + UCHAR ret = FALSE; + unsigned short IntValue; + int aneg_status; + unsigned long loop; + + PhyReset(p_mac); + + at91rm9200_EmacEnableMDIO (p_mac); + + ste100p_Deisolate(p_mac); + + at91rm9200_EmacDisableMDIO (p_mac); + + + +#if 1 + at91rm9200_EmacEnableMDIO (p_mac); + + ste100p_WaitForLink(p_mac, 500 /* timeout in ms */); + + ret = ste100p_GetLinkSpeed (p_mac); + + if (!ret) + { + ste100p_AutoNegotiate(p_mac, aneg_status); +#ifdef DEBUG_ETHER + if (aneg_status) + { + printf("link speed autonegotiated\n"); + ret = ste100p_GetLinkSpeed (p_mac); + } + else + printf("auto-neogtiation failed\n"); +#endif //DEBUG_ETHER + } + + /* Disable PHY Interrupts */ + + at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue); + udelay(1000); + /* disable all interrypts from SE100P */ + + IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE | + STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE); + + at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue); + udelay(10000); + + + + at91rm9200_EmacDisableMDIO (p_mac); + udelay(1000); +#endif + +#ifdef DEBUG_ETHER + printf("ste100p InitPhy ["); + if (ret) + printf("OK]\n"); + else + printf("FAILED]\n"); +#endif //DEBUG_ETHER + return (ret); +} + + +/* + * Name: + * ste100p_AutoNegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * TRUE - if link status set successfully + * FALSE - if link status not set + */ +UCHAR ste100p_AutoNegotiate (AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + unsigned short PhyAnar; + unsigned short PhyAnalpar; +#ifdef DEBUG_ETHER + printf("ste100p AutoNegotiate\n"); +#endif //DEBUG_ETHER +#if 1 + /* Set ste100p control register */ + if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + + value &= ~STE100P_XCR_AN; /* remove autonegotiation enable */ + value |= STE100P_XCR_ISOLATE; /* Electrically isolate PHY */ + if (!at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + + if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + + + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + PhyAnar = STE100P_ANA_NXTPG | STE100P_ANA_TXF | STE100P_ANA_TXH | + STE100P_ANA_10F | STE100P_ANA_10H | STE100P_ANA_SF; + if (!at91rm9200_EmacWritePhy (p_mac, STE100P_ANA_REG, &PhyAnar)) + return FALSE; + + /* Read the Control Register */ + if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + + value |= STE100P_XCR_SPEED | STE100P_XCR_AN | STE100P_XCR_FULL_DUP; + if (!at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + + /* Restart Auto_negotiation */ + value |= STE100P_XCR_AN; + value &= ~STE100P_XCR_ISOLATE; + value |= STE100P_XCR_RSTRT_AN; + + if (!at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + udelay(10000); + if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) + return FALSE; + + /*check AutoNegotiate complete */ + udelay (10000); + at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &value); + if (!(value & STE100P_XSR_AN_COMPLETE)) + return FALSE; + + /* Get the AutoNeg Link partner base page */ + if (!at91rm9200_EmacReadPhy (p_mac, STE100P_ANLP_REG, &PhyAnalpar)) + return FALSE; + + if ((PhyAnar & STE100P_ANA_TXF) && (PhyAnalpar & STE100P_ANLP_LPTXF)) { + /*set MII for 100BaseTX and Full Duplex */ + p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((PhyAnar & STE100P_ANA_10F) && (PhyAnalpar & STE100P_ANLP_LPTXH)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_CFG = (p_mac->EMAC_CFG & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } +#endif + return FALSE; +} + +/* + * Name: + * ste100p_DisableInterrupts + * Description: + * disables interrupts + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + */ +void ste100p_DisableInterrupts (AT91PS_EMAC p_mac) +{ + + unsigned short IntValue; + unsigned int rep; + + rep = 0; + + at91rm9200_EmacEnableMDIO (p_mac); + + /* Disable PHY Interrupts */ + + at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue); + udelay(10000); + /* disable all interrypts from SE100P */ + + IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE | + STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE); + + at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue); + udelay(10000); + + IntValue = 1; + + do + { + at91rm9200_EmacReadPhy (p_mac, STE100P_XCSIIS_REG, &IntValue); + rep++; + } while (IntValue != 0 && rep < 100); + + at91rm9200_EmacDisableMDIO (p_mac); +} + + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ diff -Naur u-boot-1.3.3/drivers/mtd/dataflash.c u-boot-1.3.3.new/drivers/mtd/dataflash.c --- u-boot-1.3.3/drivers/mtd/dataflash.c 2008-05-19 12:47:11.000000000 +0200 +++ u-boot-1.3.3.new/drivers/mtd/dataflash.c 2008-06-21 09:18:01.000000000 +0200 @@ -54,6 +54,20 @@ &dataflash_info[i].Desc); switch (dfcode) { + + case AT45DB011: + dataflash_info[i].Device.pages_number = 512; + dataflash_info[i].Device.pages_size = 264; + dataflash_info[i].Device.page_offset = 9; + dataflash_info[i].Device.byte_mask = 0x100; + dataflash_info[i].Device.cs = cs[i].cs; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i].addr; + dataflash_info[i].id = dfcode; + found[i] += dfcode;; + break; + + case AT45DB161: dataflash_info[i].Device.pages_number = 4096; dataflash_info[i].Device.pages_size = 528; @@ -178,6 +192,11 @@ if (dataflash_info[i].id != 0) { printf("DataFlash:"); switch (dataflash_info[i].id) { + + case AT45DB011: + printf("AT45DB011\n"); + break; + case AT45DB161: printf("AT45DB161\n"); break; diff -Naur u-boot-1.3.3/include/asm-arm/arch-at91rm9200/mmc.h u-boot-1.3.3.new/include/asm-arm/arch-at91rm9200/mmc.h --- u-boot-1.3.3/include/asm-arm/arch-at91rm9200/mmc.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/include/asm-arm/arch-at91rm9200/mmc.h 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AT91RM9200_MMC_H +#define __ASM_AT91RM9200_MMC_H + + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure; + u8 spec_vers; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc; + u8 read_bl_len; + u8 read_bl_partial; + u8 write_blk_misalign; + u8 read_blk_misalign; + u8 dsr_imp; + u32 c_size; + u8 vdd_r_curr_min; //Not exist in v2.0 + u8 vdd_r_curr_max; //Not exist in v2.0 + u8 vdd_w_curr_min; //Not exist in v2.0 + u8 vdd_w_curr_max; //Not exist in v2.0 + u8 c_size_mult; //Not exist in v2.0 + u8 sector_size; + u8 wp_grp_size; + u8 wp_grp_enable; + u8 default_ecc; + u8 r2w_factor; + u8 write_bl_len; + u8 write_bl_partial; + u8 copy; + u8 perm_write_protect; + u8 tmp_write_protect; + u8 file_format; + u8 file_format_grp; + u8 ecc; + u8 crc; +}; + + + + + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 +#define MMC_CMD_SD_SEND_IF_COND 8 +#define MMC_CMD_SD_READ_OCR 58 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#define MMC_ACMD_SD_SEND_IF_COND 8 + +#endif /* __ASM_AVR32_MMC_H */ diff -Naur u-boot-1.3.3/include/configs/at91boff.h u-boot-1.3.3.new/include/configs/at91boff.h --- u-boot-1.3.3/include/configs/at91boff.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/include/configs/at91boff.h 2008-06-21 09:52:58.000000000 +0200 @@ -0,0 +1,271 @@ +/* + * Lucjan Brydza + * + * Configuation settings for the AT91BOFF board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ +#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ +/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ + + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ +//#define CONFIG_USE_IRQ 1 /* we don't need IRQ/FIQ stuff */ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define MC_PUIA_VAL 0x00000000 +#define MC_PUP_VAL 0x00000000 +#define MC_PUER_VAL 0x00000000 +#define MC_ASR_VAL 0x00000000 +#define MC_AASR_VAL 0x00000000 +#define EBI_CFGR_VAL 0x00000000 +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks PLLAR not work setup by first stage loader*/ +//#define PLLAR_VAL kipa0x20263E04 /* 179.712000 MHz for PCK */ +//#define PLLBR_VAL kipa0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +//#define MCKR_VAL kiii0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +/* sdram */ +#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define PIOC_BSR_VAL 0x00000000 +#define PIOC_PDR_VAL 0xFFFF0000 +#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +//This is setup by first stage loader +//#define SDRC_CR_VAL 0x2188A159 /* set up the SDRAM 64M */ +#define SDRAM 0x20000000 /* address of the SDRAM */ +#define SDRAM1 0x20000080 /* address of the SDRAM */ +#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define SDRC_MR_VAL1 0x00000004 /* refresh */ +#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define SDRC_TR_VAL 468 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +/* + * Size of malloc() pool + */ +//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_MALLOC_LEN (136*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +#define CONFIG_BAUDRATE 115200 + +/* + * Hardware drivers + */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_DBGU +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ + +#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ + +#define CONFIG_BOOTDELAY 3 +/* #define CONFIG_ENV_OVERWRITE 1 */ + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_LOADS + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ +#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ + +#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) +#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) + +#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +/* the following are NOP's in our implementation */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 + +#define CONFIG_MISC_INIT_R +#define CONFIG_DRIVER_ETHER +#define CONFIG_NET_RETRY_COUNT 20 +//#define CONFIG_AT91C_USE_RMII +#undef CONFIG_AT91C_USE_RMII + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define CONFIG_MMC +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_NEW_PARTITION 1 +#define CONFIG_NEW_DF_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 +#define DATAFLASH_LOADER_BASE (0*264) +#define DATAFLASH_UBOOT_BASE (43*264) +#define DATAFLASH_ENV_UBOOT_BASE (510*264) +//#define DATAFLASH_KERNEL_BASE (130*1056) + +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_MAX_DATAFLASH_PAGES 4096 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ + +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_SIZE 0x100 /* 2 megs main flash */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_DATAFLASH + +#ifdef CFG_ENV_IS_IN_DATAFLASH +#define CFG_ENV_OFFSET (DATAFLASH_ENV_UBOOT_BASE) +#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE (512) /* 0x8000 */ +#else +#define CFG_ENV_IS_IN_FLASH 1 +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ +#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#else +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CFG_ENV_IS_IN_DATAFLASH */ + + +#define CFG_LOAD_ADDR 0x20200000 /* default load address */ + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ +#define CFG_U_BOOT_BASE PHYS_FLASH_1 +#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ +#else +#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ +#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) +#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "boff> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + +#define CFG_HZ 1000 +#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) +#define CONFIG_STACKSIZE_FIQ (4*1024) + +#endif + + + +#endif diff -Naur u-boot-1.3.3/include/dataflash.h u-boot-1.3.3.new/include/dataflash.h --- u-boot-1.3.3/include/dataflash.h 2008-05-19 12:47:11.000000000 +0200 +++ u-boot-1.3.3.new/include/dataflash.h 2008-06-21 09:18:01.000000000 +0200 @@ -136,6 +136,7 @@ }; /*-------------------------------------------------------------------------------------------------*/ +#define AT45DB011 0x0c #define AT45DB161 0x2c #define AT45DB321 0x34 #define AT45DB642 0x3c diff -Naur u-boot-1.3.3/include/ste100p.h u-boot-1.3.3.new/include/ste100p.h --- u-boot-1.3.3/include/ste100p.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3.new/include/ste100p.h 2008-06-21 09:18:01.000000000 +0200 @@ -0,0 +1,163 @@ +#ifndef _ste100p_h_ +#define _ste100p_h_ + + +// UTILS +#define Bit(n) (1<<(n)) + + +// STE100P register offsets. + +#define STE100P_XCR_REG 0x00 +#define STE100P_XSR_REG 0x01 +#define STE100P_PID1_REG 0x02 +#define STE100P_PID2_REG 0x03 +#define STE100P_ANA_REG 0x04 +#define STE100P_ANLP_REG 0x05 +#define STE100P_ANE_REG 0x06 +#define STE100P_XCSIIS_REG 0x11 +#define STE100P_XIE_REG 0x12 +#define STE100P_100CTR_REG 0x13 +#define STE100P_XMC_REG 0x14 + + +// STE100P XCR - Control register bit defines. +#define STE100P_XCR_RESET 0x8000 //(RW) +#define STE100P_XCR_LOOPBACK 0x4000 //(RW) +#define STE100P_XCR_SPEED 0x2000 // 1=100Meg, 0=10Meg (RW) +#define STE100P_XCR_AN 0x1000 // 1=Enable auto negotiation, 0=disable it (RW) +#define STE100P_XCR_PWRDN 0x0800 // 1=Enable power down (RW) +#define STE100P_XCR_ISOLATE 0x0400 // 1=Isolate PHY from MII (RW) +#define STE100P_XCR_RSTRT_AN 0x0200 // 1=Restart Auto Negotioation process (RW) +#define STE100P_XCR_FULL_DUP 0x0100 // 1=Enable full duplex mode, 0=half dup (RW) +#define STE100P_XCR_COLLEN 0x0080 // 1=Collision test control (RW) + +// STE100P XSR - Control status bit defines. + +#define STE100P_XSR_100T4 Bit(15) // (RO) +#define STE100P_XSR_100TX_FULL Bit(14) // (RO) +#define STE100P_XSR_100TX Bit(13) // (RO) +#define STE100P_XSR_10T_FULL Bit(12) // (RO) +#define STE100P_XSR_10T Bit(11) // (RO) +#define STE100P_XSR_MFPS Bit(6) //MF preamble suppression (RO) +#define STE100P_XSR_AN_COMPLETE Bit(5) +#define STE100P_XSR_RF Bit(4) //RF result of remote fault detection (RO/LH) +#define STE100P_XSR_AN Bit(3) //AN - auto-negotation ability, always 1 for STE100P (RO) +#define STE100P_XSR_LINK Bit(2) // Link status (RO/LL) +#define STE100P_XSR_JABBER Bit(1) // Jabber condition is detected (10Base-T only) (RO/LH) +#define STE100P_XSR_EXT Bit(0) // Extended register support, always 1 for STE100P (RO) + + +// STE100P PHY identification bit defines. + +#define STE100P_PID1_PHYID_VAL 0x1C04 // (RO) + +#define STE100P_PID2_PHYID_MASK 0xFC00 // (RO) +#define STE100P_PID2_PHYID_VAL 0x0 +#define STE100P_PID2_MODEL_MASK 0x01F0 // (RO) +#define STE100P_PID2_MODEL_VAL 0x1 +#define STE100P_PID2_REV_MASK 0x000F // (RO) +#define STE100P_PID2_REV_VAL 0x1 + +// STE100P auto-negatiation bit defines. + +#define STE100P_ANA_NXTPG Bit(15) //Next Page avability, always 0 for STE100P. (RO) +#define STE100P_ANA_RF Bit(13) // Remote fault function. (RW) +#define STE100P_ANA_FC Bit(10) // Flow Control function Ability, 1 - supports PAUSE operation of flow control for full-duplex link. (RW) +#define STE100P_ANA_T4 Bit(9) // 100Base-T4 ability, always 0 for STE100P. (RO) +#define STE100P_ANA_TXF Bit(8) // 100Base-TX full duplex ability, 1 with 100Base-TX full duplex ability. (RW) +#define STE100P_ANA_TXH Bit(7) // 100Base-TX half duplex ability, 1 with 100Base-TX half duplex ability. (RW) + +#define STE100P_ANA_10F Bit(6) // 10Base-T full duplex ability, 1 with 10Base-T full duplex ability. (RW) +#define STE100P_ANA_10H Bit(5) // 10Base-T half duplex ability, 1 with 10Base-T half duplex ability. (RW) +#define STE100P_ANA_SF 0x0000 // select field, default val 0, (RO) +#define STE100P_ANA_SF_MASK 0x000F // STE100P_ANA_SF mask + +// STE100P auto-negatiation link partner ability bit defines. + +#define STE100P_ANLP_LPNP Bit(15) // Link partner next page, 1 ON. (RO) +#define STE100P_ANLP_LPACK Bit(14) // Received link parnter ACK, 1 received. (RO) +#define STE100P_ANLP_LPRF Bit(13) // Link partner's remote fault status, 1 - remote fault detected. (RO) +#define STE100P_ANLP_LPFC Bit(10) // Link partner's flow control ability, 1 - link partner with PAUSE function full duplex link ability. (RO) +#define STE100P_ANLP_LPT4 Bit(9) // Link partner's 100Base-T4 ability, 1 - link parnter with 100Base-T4 ability. (RO) +#define STE100P_ANLP_LPTXF Bit(8) // Link partner's 100Base-TX full duplex ability, 1 - link parnter with 100Base-TX full duplex ability. (RO) +#define STE100P_ANLP_LPTXH Bit(7) // Link partner's 100Base-TX half duplex ability, 1 - link parnter with 100Base-TX half duplex ability. (RO) +#define STE100P_ANLP_LP10F Bit(6) // Link partner's 10Base-T full duplex ability, 1 - link parnter with 10Base-T full duplex ability. (RO) +#define STE100P_ANLP_LP10H Bit(5) // Link partner's 10Base-T half duplex ability, 1 - link parnter with 10Base-T half duplex ability. (RO) +#define STE100P_ANLP_LPFS 0x001F // Link partner selct field, default 0x0001 = IEEE 802.3 (RO) + +// STE100P auto-negatiation expansion bit defines. + +#define STE100P_ANE_PDF Bit(4) // Parallel detection fault, 1 - fault detecrted (RO/LH). +#define STE100P_ANE_LPNP Bit(3) // Link partner's next page ability, 1 - link partner with next page ability (RO). +#define STE100P_ANE_NP Bit(2) // STE100P next page ability, always 0 (RO). +#define STE100P_ANE_PR Bit(1) // Page received, 1 - a new page has been received (RO/LH). +#define STE100P_ANE_LPAN Bit(0) // Link partner auto-negotiation ability, 1 - LP has auto-negotiation ability (RO) + +// STE100P configuration information and interrupt status bit defines + +#define STE100P_XCIIS_SPEED Bit(9) // Configured information of SPEED, 0 - 10Mbit/s, 1 - 100Mbit/s. (RO) +#define STE100P_XCIIS_DUPLEX Bit(8) // Configured information of DUPLEX, 0 - half-duplex, 1 - full-duplex. (RO) +#define STE100P_XCIIS_PAUSE Bit(7) // Configured information of PAUSE, 0 - pause function disabled, 1 - pause function enabled. (RO) +#define STE100P_XCIIS_ANC Bit(6) // Interrupt source of auto-negotiation completed, 0 - auto-negotiation is not completed yet. (RO/LH) +#define STE100P_XCIIS_RFD Bit(5) // Interrupt source of remote fault detected, 0 -fault not detected, 1 - fault detected. (RO/LH) +#define STE100P_XCIIS_LS Bit(4) // Interrupt source link fail, 0 - link test status is up, 1 - link is down. (RO/LH). +#define STE100P_XCIIS_ANAR Bit(3) // Interrupt source of auto-negotiation ACK received, 0 - auto-negotiation not received. (RO/LH) +#define STE100P_XCIIS_PDF Bit(2) // Interrupt source of parallel detection fault, 0 - fault not detected. (RO/LH) +#define STE100P_XCIIS_ANPR Bit(1) // Interrupt source of auto-negotiation page received, 1 - auto-negotiation page os received (RO/LH) +#define STE100P_XCIIS_REF Bit(0) // Interrupt source of receive full error, 0 - the receive error number is less than 64, 1 - 64 error packets + // are received (RO/LH) + +// STE100P interrupt enable register bit defines + +#define STE100P_XIE_ANCE Bit(6) // Auto-negtiation completed interrupt enable: 0/1 - disable/enable auto-negotiation completed interrupt. (RW) +#define STE100P_XIE_RFE Bit(5) // Remote fault detected interrupt enable: 0/1 - disable/enable remote fault detection interrupt. (RW) +#define STE100P_XIE_LDE Bit(4) // Link down interrupt enable: 0/1 - disable/enable link down detection interrupt. (RW) +#define STE100P_XIE_ANAE Bit(3) // Auto-negotiation acknowledge interrupt enable: 0/1 - disable/enable link partner acknowledge interrupt. (RW) +#define STE100P_XIE_PDFE Bit(2) // Parallel detection fault interrupt enable: 0/1 - disable/enable fault parallel detection interrupt. (RW) +#define STE100P_XIE_ANPE Bit(1) // Auto-negotiation page received interrupt enable: 0/1 - disable/enable auto-negotiation page received interrupt. (RW) +#define STE100P_XIE_REFE Bit(0) // RX_ERR page full interrupt enable: 0 - disable rx_err full interrupt, 1 - enable more than 64 time rx_err interrupt (RW) + +// STE100P 100Base-TX control register bit defines + +#define STE100P_100CTR_DISRER Bit(13) // Disable the RX_ERR counter, 0 - receive error counter RX_ERR is enabled, 1 - ... disabled. (RW) +#define STE100P_100CTR_ANC Bit(12) // Auto-negotiation completed, 0 - auto-negotiation process has not completed yet, 1 - auto-negotiation process has completed. (RO) +#define STE100P_100CTR_ENRLB Bit(9) // Enable remote loop-back function: 1 - enable, 0 - disable (RW) +#define STE100P_100CTR_ENDCR Bit(8) // Enable DC restoration: 0 - disable, 1 - enable (RW) +#define STE100P_100CTR_ENRZI Bit(7) // Enable the conversions between NRZ and NRZI (RW) +#define STE100P_100CTR_EN4B5B Bit(6) // Enable 4B/5B encoder and decoder, 0 - the 4B/5B encoder and decoder are bypassed, 1 - .. enabled. (RW) +#define STE100P_100CTR_ISOTX Bit(5) // Transmit isolation: 1 - isolate from MII, 0 - for normal operation. (RW) +#define STE100P_100CTR_CMODE_MASK 0x001C // Reporting of current operation mode of transceiver: (RO) + // 000 - in auto-negotiation + // 001 - 10Base-T half duplex + // 010 - 100Base-TX half duplex + // 011 - reserved + // 100 - reserved + // 101 - 10Base-T full duplex + // 110 - 100Base-TX full duplex + // 111 - isolation, auto-negotiation disable +#define STE100P_100CTR_DISMLT Bit(1) // Disable MLT3, 0 - encoder/decoder enabled, 1 - ... disabled, (RW) +#define STE100P_100CTR_DISCRM Bit(0) // Disable Scramble, 0 - scrambler/descambler enabled, 1 - scrambler/descambler disabled, (RW) + + +// STE100P mode control register bit defines + +#define STE100P_XMC_LD Bit(11) // Long distance mode of 10Base-T: 0 - notmal squelch level, 1 - reduces squelch for extended cable lenght. (RW) +#define STE100P_XMC_PAD_MASK 0x00F8 // PHY addres 4:0 - 0x0000 after reset causes to isolate the PHY from MII (PR0 - 10 bit is set) (RW). +#define STE100P_XMC_MFPSE Bit(1) // MF preamble supression enable, 1 - accept management frames with pre-amble supressed. (RW) + + +/* (R0) - register is rea-only. + * (RW) - register is rea-write. + * (LH) - latching high and cleared by reading. + * (LL) - latching low and cleared by reading. + */ + +unsigned int ste100p_IsPhyConnected (AT91PS_EMAC p_mac); +unsigned int ste100p_Isolate (AT91PS_EMAC p_mac); +void ste100p_DisableInterrupts (AT91PS_EMAC p_mac); +UCHAR ste100p_GetLinkSpeed (AT91PS_EMAC p_mac); +UCHAR ste100p_InitPhy (AT91PS_EMAC p_mac); +UCHAR ste100p_AutoNegotiate (AT91PS_EMAC p_mac, int *status); + +#endif // _ste100p_h_ diff -Naur u-boot-1.3.3/Makefile u-boot-1.3.3.new/Makefile --- u-boot-1.3.3/Makefile 2008-05-19 12:47:11.000000000 +0200 +++ u-boot-1.3.3.new/Makefile 2008-06-21 09:18:01.000000000 +0200 @@ -2332,6 +2332,8 @@ at91rm9200dk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200 +at91boff_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t at91boff NULL at91rm9200 cmc_pu2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200